1. Field of the Invention
The present invention relates to disk drives. In particular, the present invention relates to a disk drive employing enhanced instruction cache management to facilitate non-sequential immediate operands.
2. Description of the Prior Art
A disk drive typically comprises a microprocessor executing instructions of a program 11 stored in a memory, wherein a memory controller reads the instructions from the memory and provides the instructions to the microprocessor. The memory is typically implemented as a separate chip, such as a dynamic random access memory (DRAM), which provides substantial storage capacity at minimal cost. Stand alone memory chips, such as DRAM, are typically “burst access” devices meaning they operate at optimal speed if blocks of memory are accessed sequentially. This is due to the setup and arbitration time required for the first access, after which subsequent sequential access times are significantly shorter.
If a non-sequential instruction is encountered during the execution of a program, the processing speed is reduced due to the latency in accessing the first instruction in the following sequence of instructions. For example, if a branch instruction is encountered there is a delay associated with accessing the first instruction following the branch. Prior art techniques have employed a cache memory (e.g., a static random access memory (SRAM)) integrated into a chip with the microprocessor for caching the sequence of instructions associated with a branch instruction, such as a branch instruction at the end of a loop. The cache memory has no setup or arbitration delay so that the cached instructions within the loop can be executed immediately, thereby avoiding the delay associated with the external memory. When the loop terminates, a “cache miss” occurs causing the cache memory to be flushed and refilled with the instructions following the loop.
Certain microprocessors (e.g., certain ARM microprocessors) employ a fixed length instruction set wherein an immediate operand (a constant) may be implemented as a non-sequential instruction. If a non-sequential immediate operand results in a cache miss causing the instruction cache to be flushed, processing performance will degrade. The memory controller will fill the instruction cache with instructions following the immediate operand which are not the next instructions to be executed. This results in yet another cache miss further increasing the processing delay associated with flushing and refilling the instruction cache.
There is, therefore, a need to improve processing speed in a computer system that implements an immediate operand as a non-sequential instruction.